SH7730 Datasheet, PDF (498/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 13.1.
XTAL
EXTAL
MD1, MD0
Crystal
oscillation
circuit
Divider 3
(×1/1024)
PLL circuit
(×2 to ×16)
Divider 1
(×1/2)
CKO
Divider 2
(×1/1)
(×1/2)
(×1/3)
(×1/4)
(×1/6)
(×1/8)
(×1/10)
(×1/12)
(×1/16)
(×1/20)
RCLK
CPU clock
(Iφ)
SH clock
(Sφ)
Bus clock
(Bφ)
Peripheral clock
(Pφ)
IrDA clock
(SCLK)
Oscillation
circuit
Multiplication
control
Division
control
Stop control
FRQCR
PLLCR
OSCWTCR
IrDACLKCR
STBCR
Peripheral bus interface
Control
circuit
Peripheral bus
[Legend]
FRQCR: Frequency control register
IrDACLKCR: IrDA clock control register
PLLCR: PLL control register
OSCWTCR: Oscillation settling time watch timer control register
STBCR: ^{Standby control register (For details, see section 14, Reset and Power-Down Modes.)}
Figure 13.1 Block Diagram of CPG
Rev. 1.00 Sep. 19, 2007 Page 450 of 1136
REJ09B0359-0100