SH7730 Datasheet, PDF (511/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
13.7 Notes on Board Design
(1) Bypass Capacitor
Insert about 0.1 to 1.0 µF of laminated ceramic capacitors as bypass capacitors for each V_SS/V_CC
pair. Table 13.5 shows the pair of power supply pins. Mount the bypass capacitor near the power
supply pins of the LSI. Use components with a frequency characteristic suitable for the operating
frequency of the LSI, as well as a suitable capacitance value.
Table 13.5 Pairs of Power Supply Pins
Paired Power Supply Name
AVcc – AVss
Vcc – Vss
Vcc_PLL1 – VSS_PLL1
Vcc_PLL2 – VSS_PLL2
VccQ - VssQ
Paired Power Supply Pin No.
205 - 208
29 - 27, 81 - 79, 134 - 132, 154 - 152, 175 - 173
145 - 147
150 - 148
3 - 6, 21 - 19, 35 - 33, 47 - 45, 59 - 57, 71 - 69, 85 - 83,
97 - 95, 111 - 109, 163 - 161, 183 - 181, 183 - 198
(2) When Using a PLL Oscillator Circuit
Keep the wiring from the PLL V_CC and V_SS connection pattern to the power supply pins short, and
make the pattern width large, to minimize the inductance component.
The analog power supply system of the PLL circuit is sensitive to noise. Therefore system
malfunction may occur by the intervention with another power supply. Do not supply the analog
power supply with the same resource as the digital power supply of V_DD and V_CCQ.
Avoid crossing
signal lines
VDD_PLL2
Vss_PLL2
VDD_PLL1
Power
Vcc ^supply
Vss
Vss_PLL1
Figure 13.2 Points to Note in Use of the PLL Oscillator Circuit
Rev. 1.00 Sep. 19, 2007 Page 463 of 1136
REJ09B0359-0100