SH7730 Datasheet, PDF (326/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
4. SDRAM interface
• Can set the SDRAM in up to two areas.
• Multiplex output for row address/column address.
• Efficient access by single read/single write.
• High-speed access by bank-active mode.
• Supports an auto-refresh and self-refresh.
• Supports low-power function.
5. Byte-selection SRAM interface
• Can connect directly to a byte-selection SRAM.
6. PCMCIA interface
• Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver. 4.2
(PCMCIA2.1 Rev 2.1).
• Controls the insertion of the wait state using software.
• Supports the bus sizing function of the I/O bus width (only in little endian mode).
7. Bus arbitration
• Outputs a bus acknowledge after receiving a bus request from an external device.
8. Refresh function
• Supports the auto-refresh and self-refresh functions.
• Specifies the refresh interval using the refresh counter and clock selection.
• Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
9. Interval timer using refresh counter
• Generates an interrupt request by a compare match.
Note: The PCMCIA interface provided by the BSC only supports the signals and bus protocols
shown in table 11.1.
Rev. 1.00 Sep. 19, 2007 Page 278 of 1136
REJ09B0359-0100