SH7730 Datasheet, PDF (684/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
21.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RDLE — — —
RDLA[3:0]
RDRE — — —
RDRA[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
15
RDLE
0
R/W
14 to 12 —
All 0 R
11 to 8 RDLA[3:0] 0000 R/W
7
RDRE
0
R/W
6 to 4 —
All 0 R
3 to 0 RDRA[3:0] 0000 R/W
Description
Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
Rev. 1.00 Sep. 19, 2007 Page 636 of 1136
REJ09B0359-0100