SH7730 Datasheet, PDF (607/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 18 Timer Unit (TMU)
18.4.3 Interrupt Sources and Priorities
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. A specific code is set in the
interrupt event register (INTEVT) for this interrupt and interrupt processing must be executed
according to the code.
The priorities between channels are changeable by the interrupt controller. For details, see section
5, Exception Handling, and section 10, Interrupt Controller (INTC). Table 18.3 lists TMU
interrupt sources.
Table 18.3 TMU Interrupt Sources
Channel
0
1
2
Interrupt Source
TUNI0
TUNI1
TUNI2
Description
Underflow interrupt 0
Underflow interrupt 1
Underflow interrupt 2
Priority
High
Low
18.5 Usage Notes
18.5.1 Writing to Registers
Synchronization processing is not performed for timer counting during register writes. When
writing to registers, be sure to clear the start bits (STR2 to STR0) of the channel in TSTR and halt
the timer counting.
18.5.2 Reading Registers
Synchronization processing is performed for timer counting during register reads. When the timer
counting and register read are performed simultaneously, the register value stored before the
TCNT countdown is read through the synchronization processing.
Rev. 1.00 Sep. 19, 2007 Page 559 of 1136
REJ09B0359-0100