SH7730 Datasheet, PDF (43/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Table 11.9
Table 11.10
Table 11.11
Table 11.12
Table 11.13
Table 11.14
Table 11.15
Table 11.15
Table 11.16
Table 11.16
Table 11.17
Table 11.18
Table 11.18
Table 11.19
Table 11.19
Table 11.20
Table 11.20
Table 11.21
Table 11.22
Table 11.23
Table 11.24
Table 11.25
32-Bit External Device/Big Endian Access and Data Alignment ......................... 330
16-Bit External Device/Big Endian Access and Data Alignment ..................... 331
8-Bit External Device/Big Endian Access and Data Alignment....................... 332
32-Bit External Device/Little Endian Access and Data Alignment .................. 333
16-Bit External Device/Little Endian Access and Data Alignment .................. 334
8-Bit External Device/Little Endian Access and Data Alignment .................... 335
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-1........................................................................ 348
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-2........................................................................ 349
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-1........................................................................ 350
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-2........................................................................ 351
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (3) ........................................................................... 352
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (4)-1........................................................................ 353
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (4)-2........................................................................ 354
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (5)-1........................................................................ 355
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (5)-2........................................................................ 356
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (6)-1........................................................................ 357
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (6)-2........................................................................ 358
Relationship between A3BSZ[1:0], A3ROW[1:0], A3COL[1:0], and
Address Multiplex Output (7) ........................................................................... 359
Relationship between Access Size and Number of Bursts................................ 360
Access Address in SDRAM Mode Register Write ........................................... 379
Output Addresses when EMRS Command is Issued ........................................ 381
Relationship between Bus Width, Access Size, and Number of Bursts............ 384
Section 12 Direct Memory Access Controller (DMAC)
Table 12.1 Pin Configuration.................................................................................................. 405
Table 12.2 Register Configuration of DMAC......................................................................... 406
Table 12.3 State of Registers in Each Operating Mode .......................................................... 408
Table 12.4 Transfer Request Sources ..................................................................................... 426
Table 12.5 Selecting External Request Detection by DL and DS Bits ................................... 428
Rev. 1.00 Sep. 19, 2007 Page xliii of xlviii