SH7730 Datasheet, PDF (773/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Initial
Bit
Bit Name Value R/W Description
3
STOP
0
R/W Stop Bit Length
Selects one or two bits as the stop bit length.
In receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
2
—
This setting is only valid in asynchronous mode. In
synchronous mode, this setting is invalid since stop bits
are not added.
0: One stop bit*¹
1: Two stop bits*²
Notes: 1. In transmitting, a single bit of 1 is added at
the end of each transmitted character.
2. In transmitting, two bits of 1 are added at
the end of each transmitted character.
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
CKS[1:0] 00
R/W Clock Select
These bits select the internal clock source of the on-
chip baud rate generator.
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: Pφ is the peripheral clock.
Note: In synchronous mode, bits other than CKS[1:0] are fixed to 0.
Rev. 1.00 Sep. 19, 2007 Page 725 of 1136
REJ09B0359-0100