SH7730 Datasheet, PDF (658/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 21 Serial I/O with FIFO (SIOF)
Figure 21.1 shows a block diagram of the SIOF.
SIOF interrupt
request
Bus interface
Peripheral bus
Control
registers
Pφ
1/nMCLK
Baud rate
generator
Timing
control
Transmit
FIFO
(32 bits x16
stages)
Receive
FIFO
(32 bits x16
stages)
Transmit control
data
Receive control
data
P/S
S/P
SIOFMCK
SIOFSCK SIOFSYNC
SIOFTXD
Figure 21.1 Block Diagram of SIOF
SIOFRXD
21.2 Input/Output Pins
The pin configuration in this module is shown in table 21.1.
Table 21.1 Pin Configuration
Pin Name
Abbreviation* I/O
Description
SIOF_MCK SIOFMCK
Input
Master clock input
SIOF_SCK SIOFSCK
I/O
Serial clock (common to transmission/reception)
SIOF_SYNC SIOFSYNC
I/O
Frame synchronization signal
(common to transmission/reception)
SIOF_TXD
SIOFTXD
Output Transmit data
SIOF_RXD SIOFRXD
Input
Receive data
Note: * In the following descriptions, SIOFMCK, SIOFSCK, SIOFSYNC, SIOFTXD, and
SIOFRXD are used as generic names.
Rev. 1.00 Sep. 19, 2007 Page 610 of 1136
REJ09B0359-0100