SH7730 Datasheet, PDF (533/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 15 RCLK Watchdog Timer (RWDT)
15.3.1 RCLK Watchdog Timer Counter (RWTCNT)
RWTCNT is an 8-bit readable/writable register that increments on the selected clock. When an
overflow occurs, it generates a power-on reset. The RWTCNT counter is initialized to H'00 by a
power-on reset (including RWDT overflow reset.) Use a word access to write to the RWTCNT
counter, with H'5A in the upper byte. Use a byte access to read RWTCNT.
Bit: 7
6
5
4
3
2
1
0
RWTCNT
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
15.3.2 RCLK Watchdog Timer Control/Status Register (RWTCSR)
RWTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, overflow flags, and enable bit.
RWTCSR is initialized to H'87 by a power-on reset (including RWDT overflow reset). Use a word
access to write to RWTCSR, with H'A5 in the upper byte. Use a byte access to read RWTCSR.
BIt: 7
6
5
4
3
TME
—
WR
FLG
WOVF
—
Initial value: 1* 0
0
0
0
R/W: R/W R R R/W R
2
1
0
CKS[2:0]
1
1
1
R/W R/W R/W
Bit
Bit Name Initial Value R/W Description
7
TME
1*
R/W Starts and stops timer operation.
0: Timer disabled: Count-up stops and RWTCNT value
is retained
1: Timer enabled
6
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 485 of 1136
REJ09B0359-0100