SH7730 Datasheet, PDF (50/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 1 Overview
The features of this LSI are listed in table 1.1.
Table 1.1 Features of This LSI
Item
CPU
Features
• Renesas Technology original architecture
• Upward compatible with SH-1, SH-2, SH-3, and SH4 at instruction set level
• 32-bit internal data bus
• General-register files
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Seven 32-bit control registers
 Four 32-bit system registers
• RISC-type instruction set (upward compatible with SH-1, SH-2, SH-3, and
SH4
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instructions
 Instructions executed with conditions
 Instruction set based on the C language
• Super scalar design which executes two instructions simultaneously
• Instruction execution time: Two instructions per cycle (max.)
• Virtual address space: 4 Gbytes
• Space identifier ASID: 8 bits, 256 virtual address spaces
• Built-in multiplier
• Eight-stage pipeline
Rev. 1.00 Sep. 19, 2007 Page 2 of 1136
REJ09B0359-0100