SH7730 Datasheet, PDF (499/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 13 Clock Pulse Generator (CPG)
The CPG blocks function as follows:
(1) PLL Circuit
The PLL circuit multiples the clock frequency input from the EXTAL pin by the ratio of ×2 to
×16. The multiplication ratio is set by the frequency control register (FRQCR). Turning on and off
the PLL circuit is set by the PLL control register (PLLCR).
(2) Divider 1
Divider 1 divides the clock frequency input from the EXTAL pin by two. The clock signal from
divider 1 is input to divider 2 when the PLL circuit is off.
(3) Divider 2
Divider 2 receives the clock signal from divider 1 or the PLL circuit as an input and generates the
CPU clock, SH clock, bus clock, and peripheral clock. The division ratios are set by the respective
frequency control registers.
(4) Divider 3
Divider 3 divides the clock frequency input from the EXTAL pin by 1024.
(5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD0 and MD1 pins
and the frequency control register (FRQCR).
(6) Standby Control Circuit
The standby control circuit controls the state of the on-chip oscillation circuit and other modules
during clock switching and in sleep mode or standby mode.
(7) Frequency Control Register (FRQCR)
The frequency control register has bits for setting the multiplication ratio of the PLL circuit, and
the frequency division ratio for the CPU clock, SH clock, bus clock, and peripheral clock.
(8) Standby Control Register (STBCR)
The standby control register has bits for controlling the power-down modes. See section 14, Reset
and Power-Down Modes for details on the standby control register.
Rev. 1.00 Sep. 19, 2007 Page 451 of 1136
REJ09B0359-0100