SH7730 Datasheet, PDF (19/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

20.3.3 I²C Bus Mode Register (ICMR) ............................................................................. 582
20.3.4 I²C Bus Interrupt Enable Register (ICIER) ............................................................ 584
20.3.5 I²C Bus Status Register (ICSR) .............................................................................. 586
20.3.6 Slave Address Register (SAR) ............................................................................... 589
20.3.7 I²C Bus Transmit Data Register (ICDRT).............................................................. 589
20.3.8 I²C Bus Receive Data Register (ICDRR) ............................................................... 590
20.3.9 I²C Bus Shift Register (ICDRS) ............................................................................. 590
20.3.10 NF2CYC Register (NF2CYC) ............................................................................... 591
20.4 Operation .......................................................................................................................... 592
20.4.1 I²C Bus Format ....................................................................................................... 592
20.4.2 Master Transmit Operation .................................................................................... 593
20.4.3 Master Receive Operation...................................................................................... 595
20.4.4 Slave Transmit Operation....................................................................................... 597
20.4.5 Slave Receive Operation ........................................................................................ 599
20.4.6 Noise Filter............................................................................................................. 601
20.4.7 Example of Use ...................................................................................................... 602
20.5 Interrupt Requests ............................................................................................................. 606
20.6 Bit Synchronous Circuit.................................................................................................... 607
20.7 Usage Notes ...................................................................................................................... 608
20.7.1 Restriction on the Setting of Transfer Rate in Multi-Master Operation ................. 608
20.7.2 Restriction on the Use of Bit-Operation Instructions to Set MST and TRS in
Multi-Master Operation.......................................................................................... 608
Section 21 Serial I/O with FIFO (SIOF)............................................................609
21.1 Features............................................................................................................................. 609
21.2 Input/Output Pins.............................................................................................................. 610
21.3 Register Descriptions........................................................................................................ 611
21.3.1 Mode Register (SIMDR)........................................................................................ 613
21.3.2 Control Register (SICTR) ...................................................................................... 616
21.3.3 Transmit Data Register (SITDR) ........................................................................... 619
21.3.4 Receive Data Register (SIRDR)............................................................................. 620
21.3.5 Transmit Control Data Register (SITCR) .............................................................. 621
21.3.6 Receive Control Data Register (SIRCR)................................................................ 622
21.3.7 Status Register (SISTR) ......................................................................................... 623
21.3.8 Interrupt Enable Register (SIIER).......................................................................... 629
21.3.9 FIFO Control Register (SIFCTR) .......................................................................... 631
21.3.10 Clock Select Register (SISCR) .............................................................................. 633
21.3.11 Transmit Data Assign Registers (SITDAR) .......................................................... 634
21.3.12 Receive Data Assign Register (SIRDAR).............................................................. 636
21.3.13 Control Data Assign Register (SICDAR) .............................................................. 637
Rev. 1.00 Sep. 19, 2007 Page xix of xlviii