SH7730 Datasheet, PDF (224/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 7 Memory Management Unit (MMU)
EPR[2]: Reading in user mode
EPR[1]: Writing in user mode
EPR[0]: Execution in user mode (instruction fetch)
• C: Cacheability bit
Indicates whether a page is cacheable.
0: Not cacheable
1: Cacheable
When the control register area is mapped, this bit must be cleared to 0.
• D: Dirty bit
Indicates whether a write has been performed to a page.
0: Write has not been performed.
1: Write has been performed.
• WT: Write-through bit
Specifies the cache write mode.
0: Copy-back mode
1: Write-through mode
Rev. 1.00 Sep. 19, 2007 Page 176 of 1136
REJ09B0359-0100