SH7730 Datasheet, PDF (887/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
25.4.3 Register Settings
Table 25.4 shows a map of the bits in the registers used by the smart card interface.
Bits for which 0 or 1 is shown must always be set to the value shown. The method for setting the
bits other than these is explained below.
Table 25.4 Register Settings for Smart Card Interface
Register
SCSMR
SCBRR
SCSCR
SCTDR
SCSSR
SCRDR
SCSCMR
SCSC2R
SCWAIT
SCGRD
SCSMPL
SCDMAEN
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
1
O/E
0
0
0
0
0
0
0
0
BRR2
BRR1
TIE
RIE
TE
RE
WAIT_IE TEIE
CKE1
SCTDR7 SCTDR6 SCTDR5 SCTDR4 SCTDR3 SCTDR2 SCTDR1
TDRE RDRF ORER ERS
PER
TEND WAIT_ER
SCRDR7 SCRDR6 SCRDR5 SCRDR4 SCRDR3 SCRDR2 SCRDR1
HOEN LCB
PB
WECC SDIR
SINV
RST
EIO
0
0
0
0
0
0
SCWAIT15 to SCWAIT0
SCGRD7 to SCGRD0
SCSMPL10 to SCSMPL0, bits 15 to 11 are 0
RDMAE TDMAE 0
0
0
0
0
Bit 0
0
BRR0
CKE0
SCTDR0
0
SCRDR0
SMIF
0
0
(1) Serial Mode Register (SCSMR) Setting
When the IC card is set for the direct convention, the O/E bit is cleared to 0; for the inverse
convention, it is set to 1.
(2) Bit Rate Register (SCBRR) Setting
Sets the bit rate. For the method of computing settings, refer to section 25.4.4, Clocks.
(3) Serial Control Register (SCSCR) Settings
Each interrupt can be enabled and disabled using the TIE, RIE, TEIE, and WAIT_IE bits.
By setting either the TE or RE bit to 1, transmission or reception is selected.
Rev. 1.00 Sep. 19, 2007 Page 839 of 1136
REJ09B0359-0100