SH7730 Datasheet, PDF (601/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 18 Timer Unit (TMU)
18.2.2 Timer Control Registers (TCR)
TCR are 16-bit readable/writable registers that control the timer counters (TCNT) and interrupts.
TCR control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow
has been set to 1, and also carry out counter clock selection.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — UNF — — UNIE — —
TPSC[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R/(W)* R R R/W R R R/W R/W R/W
Initial
Bit
Bit Name Value
15 to 9 —
All 0
8
UNF
0
7, 6 —
All 0
5
UNIE
0
4, 3 —
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Underflow Flag
Status flag that indicates occurrence of a TCNT underflow.
0: TCNT has not underflowed
[Clearing condition]
0 is written to UNF
1: TCNT has underflowed
[Setting condition]
TCNT underflows
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Underflow Interrupt Control
Controls enabling of interrupt generation when the status
flag (UNF) indicating TCNT underflow has been set to 1.
0: Interrupt due to UNF (TUNI) is disabled
1: Interrupt due to UNF (TUNI) is enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 553 of 1136
REJ09B0359-0100