SH7730 Datasheet, PDF (814/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
(d) Simultaneous Serial Data Transmission and Reception
Figures 23.20, and 23.21 show sample flowcharts for simultaneous serial transmission and
reception.
Start of simultaneous
transmission/reception
Set receive trigger number in
RTRG[1:0] in SCAFCR
1
Write remaining transmit data
2
to SCAFTDR
Read TDFE and RDF bits in SCASSR
TDFE =1?
RDF =1?
No
Yes
Write 0 to TDFE and RDF bits in
SCASSR after reading 1 from them
Set TE and RE bits in SCASCR
simultaneously
When using transmit FIFO data interrupt,
set TIE bit to 1
3
When using receive FIFO data interrupt,
set RIE bit to 1
1. Set the receive trigger number
in SCAFCR.
2. Write the remaining transmit data
to SCAFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCASSR,
and if 1, clear to 0.
3. Transmission/reception is started
when the TE and RE bits in SCASCR
are set to 1. The TE and RE bits
must be set simultaneously.
4. After the end of transmission/reception,
clear the TE and RE bits to 0.
TDFE =1?
RDF =1?
No
Yes
Read receive trigger number of receive
data bytes from SCAFRDR
Clear TE and RE bits in SCASCR to 0 4
End of
transmission/reception
Figure 23.20 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
(First Transfer after Initialization)
Rev. 1.00 Sep. 19, 2007 Page 766 of 1136
REJ09B0359-0100