SH7730 Datasheet, PDF (910/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 26 A/D Converter
26.3.2 A/D Control/Status Registers (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'0000 by a reset and in standby mode.
Bit: 15 14 13 12 11 10 9
ADF ADIE ADST DMASL TRGE[1:0] —
Initial value: 0
0
0
0
0
0
0
R/W:R/(W)* R/W R/W R/W R/W R/W R
8
7
6
5
4
3
2
1
0
— CKS[1:0] MULTI[1:0] —
CH[2:0]
0
0
1
0
0
0
0
0
0
R R/W R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
ADF
0
R/(W)* A/D End Flag
Indicates the end of A/D conversion.
[Clearing conditions]
(1) Cleared by reading ADF while ADF = 1, then writing
0 to ADF
(2) Cleared when DMAC is activated by ADI interrupt
and ADDR is read
[Setting conditions]
• Single mode: A/D conversion ends
• Multi mode: A/D conversion ends cycling through
the selected channels
• Scan mode: A/D conversion ends cycling through
the selected channels
Note: Clear this bit by writing 0.
14
ADIE
0
R/W A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at the
end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
Rev. 1.00 Sep. 19, 2007 Page 862 of 1136
REJ09B0359-0100