SH7730 Datasheet, PDF (517/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
14.3.2 Module Stop Register 0 (MSTPCR0)
MSTPCR0 is a 32-bit readable/writable register that can individually start or stop the module
assigned to each bit.
MSTPCR0 can be accessed only in longwords.
After cancelling module stop mode for the instruction cache (IC), operand cache (OC), TLB, or IL
memory, either of the following preprocessing must be performed before accessing these modules.
Note that such module access includes instruction fetch from a relevant module and instruction
fetch using a relevant module.
• After reading the changed MSTPn bit once, execute the RTE instruction.
• After reading the changed MSTPn bit once, execute the ICBI instruction for any address. The
address can be in a non-cacheable area.
Bit: 31 30 29 28 27 26
MSTP0 MSTP0 MSTP0
31
30
29
—
MSTP0
27
—
Initial value: 0
0
0
0
0
0
R/W: R/W R/W R/W R R/W R
25 24 23 22 21 20 19 18 17 16
—
MSTP0
24
—
MSTP0 MSTP0
22
21
—
MSTP0 MSTP0 MSTP0 MSTP0
19
18
17
16
0
0
0
0
0
0
0
0
0
0
R R/W R R/W R/W R R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
MSTP0 MSTP0 MSTP0
15
14
13
—
—
—
MSTP0 MSTP0 MSTP0 MSTP0 MSTP0 MSTP0
09 08 07 06 05 04
—
MSTP0
02
—
—
Initial value: 0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R R/W R R
Initial
Bit
Bit Name Value R/W Description
31
MSTP031 0
R/W Module Stop Bit 031
Setting this bit to 1 halts supply of the clock signal to
the TLB.
0: TLB operates
1: Clock supply to TLB halted
30
MSTP030 0
R/W Module Stop Bit 030
Setting this bit to 1 halts supply of the clock signal to
the instruction cache (IC).
0: IC operates
1: Clock supply to IC halted
Rev. 1.00 Sep. 19, 2007 Page 469 of 1136
REJ09B0359-0100