SH7730 Datasheet, PDF (20/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

21.4 Operation .......................................................................................................................... 639
21.4.1 Serial Clocks .......................................................................................................... 639
21.4.2 Serial Timing ......................................................................................................... 640
21.4.3 Transfer Data Format ............................................................................................. 641
21.4.4 Register Allocation of Transfer Data ..................................................................... 643
21.4.5 Control Data Interface............................................................................................ 645
21.4.6 FIFO....................................................................................................................... 647
21.4.7 Transmit and Receive Procedures .......................................................................... 649
21.4.8 Interrupts ................................................................................................................ 654
21.4.9 Transmit and Receive Timing................................................................................ 656
Section 22 Serial Communication Interface with FIFO (SCIF)........................ 661
22.1 Features............................................................................................................................. 661
22.2 Input/Output Pins.............................................................................................................. 664
22.3 Register Descriptions........................................................................................................ 665
22.3.1 Receive Shift Register (SCRSR)............................................................................ 668
22.3.2 Receive FIFO Data Register (SCFRDR) ............................................................... 668
22.3.3 Transmit Shift Register (SCTSR) .......................................................................... 669
22.3.4 Transmit FIFO Data Register (SCFTDR) .............................................................. 669
22.3.5 Serial Mode Register (SCSMR)............................................................................. 669
22.3.6 Serial Control Register (SCSCR)........................................................................... 673
22.3.7 Serial Status Register (SCFSR).............................................................................. 677
22.3.8 Bit Rate Register (SCBRR).................................................................................... 685
22.3.9 FIFO Control Register (SCFCR) ........................................................................... 686
22.3.10 FIFO Data Count Set Register (SCFDR) ............................................................... 689
22.3.11 Line Status Register (SCLSR) ............................................................................... 690
22.4 Operation .......................................................................................................................... 691
22.4.1 Overview................................................................................................................ 691
22.4.2 Operation in Asynchronous Mode ......................................................................... 693
22.4.3 Operation in Clock Synchronous Mode ................................................................. 703
22.5 SCIF Interrupt Sources and DMAC.................................................................................. 710
22.6 Usage Notes ...................................................................................................................... 711
22.6.1 SCFTDR Writing and TDFE Flag ......................................................................... 711
22.6.2 SCFRDR Reading and RDF Flag........................................................................... 711
22.6.3 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ....... 711
22.6.4 Using the DMAC ................................................................................................... 713
22.6.5 Interrupts ................................................................................................................ 713
Rev. 1.00 Sep. 19, 2007 Page xx of xlviii