SH7730 Datasheet, PDF (466/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Bit
13, 12
Initial
Bit Name Value
SM[1:0] 00
11 to 8 RS[3:0] 0000
R/W Descriptions
R/W Source Address Mode
Specify whether the DMA source address is
incremented, decremented, or left fixed.
00: Fixed source address
Since the address set in SAR is not modified, the
same address is output in the second and
subsequent transfers. The address is incremented
at the first and second transfers in 16/32-byte
division transfer mode.
01: Source address is incremented
+1 in byte units transfer
+2 in word units transfer
+4 in longword units transfer
+8 in 8-byte units transfer
+16 in 16-byte units transfer
+32 in 32-byte units transfer
10: Source address is decremented
–1 in byte units transfer
–2 in word units transfer
–4 in longword units transfer
Setting prohibited in 8/16/32-byte units transfer
11: Fixed source address
Set to prevent an address from being changed in the
objective modules. The address is not changed
even in 16/32-byte division transfer mode.
Example: When specifying FIFOs in the external
devices and peripheral modules.
R/W Resource Select
Specify which transfer requests will be sent to the
DMAC. The changing of transfer request source should
be done in the state that the DMA enable bit (DE) is set
to 0.
0000: External request
0100: Auto request
1000: Selected by DMA extended resource selector
(DMARS)
Other than above: Setting prohibited
Note: External request specification is valid only in
CHCR_0 and CHCR_1. External request cannot
be selected in CHCR_2 to CHCR_5.
Rev. 1.00 Sep. 19, 2007 Page 418 of 1136
REJ09B0359-0100