SH7730 Datasheet, PDF (471/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
1
NMIF
0
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1.
When the NMI is input, the DMA transfer in progress can
be done in at least one transfer unit. When the DMAC is
not in operational, the NMIF bit is set to 1 even if the NMI
interrupt was input.
0: No NMI interrupt
[Clearing condition]
• Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
0
DME
0
R/W DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, transfer is
enabled. In this time, all of the bits TE in CHCR, NMIF,
and AE in DMAOR must be 0. If this bit is cleared during
transfer, transfers in all channels are terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note: * Writing 0 is possible to clear the flag.
12.3.9 DMA Extended Resource Selectors (DMARS0 to DMARS2)
DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of SCIF, SCIFA, SIOF, IrDA, SIM, ADC, and CMT.
When MID/RID other than the values listed in table 12.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits RS[3:0]
has been set to B'1000 for CHCR_0 to CHCR_5 registers. Otherwise, even if DMARS has been
set, transfer request source is not accepted.
Rev. 1.00 Sep. 19, 2007 Page 423 of 1136
REJ09B0359-0100