SH7730 Datasheet, PDF (778/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.3.7 FIFO Error Count Register (SCAFER)
SCAFER is a 16-bit read-only register that indicates the number of receive data errors (framing
error/parity error).
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
——
PER[5:0]
——
FER[5:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
15,14
Bit Name

13 to 8 PER[5:0]
7, 6

5 to 0 FER[5:0]
Initial
Value
All 0
All 0
All 0
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Parity Error
Indicate the number of data bytes which contain parity
errors in receive data stored in SCAFRDR in
asynchronous mode.
PER[5:0] indicate the number of data bytes with parity
errors after the ER bit in SCASSR is set.
If all 64-byte receive data in SCAFRDR have parity
errors, bits PER[5:0] are all 0s.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R
Framing Error
Indicate the number of data bytes which contain
framing errors in receive data stored in SCAFRDR in
asynchronous mode.
FER[5:0] indicate the number of data bytes with
framing errors after the ER bit in SCASSR is set.
If all 64-byte receive data in SCAFRDR have framing
errors, bits FER[5:0] are all 0s.
Rev. 1.00 Sep. 19, 2007 Page 730 of 1136
REJ09B0359-0100