SH7730 Datasheet, PDF (346/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
10, 9
BSZ[1:0] 11*
R/W Data Bus Width
Specify the data bus width of spaces.
00: Setting prohibited
01: 8 bits
10: 16 bits
11: 32 bits
Notes: 1. The data bus width for area 0 is specified by
the external pin. The BSZ[1:0] bit setting in
CS0BCR is ignored.
2. If area 5 or area 6 is specified as PCMCIA
space, the bus width can be specified as
either 8 bits or 16 bits.
3. If area 2 or area 3 is specified as SDRAM
space, the bus width can be specified as
either 16 bits or 32 bits.
8 to 0 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * CS0BCR samples the external pins (MD3 and MD4) that specify the bus width at
power-on reset.
Rev. 1.00 Sep. 19, 2007 Page 298 of 1136
REJ09B0359-0100