SH7730 Datasheet, PDF (525/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 14 Reset and Power-Down Modes
14.4 Operation
14.4.1 Reset
(1) Power-on reset
Reset this LSI chip by using the power-on reset to recommence execution from the initial state and
when power is initially supplied. The RESETP pin is used for the power-on reset. A power-on
reset discontinues all processing in execution, all pending processing for events, and is
immediately followed by reset processing with the RESETOUT pin driven low. The conditions for
generating a power-on reset are as follows.
1. A low level is input on the RESETP pin.
2. When the RWDT starts counting and the counter overflows.
(2) H-UDI reset
When the H-UDI reset assertion command is sent to the H-UDI pins, the system enters the same
state as a power-on reset. See section 31, User Debugging Interface (H-UDI) for details on the H-
UDI reset.
(3) Manual reset
A manual reset is generated by software. See section 5, Exception Handling for details on the
manual reset. RESETOUT pin level does not become low on manual reset.
(4) Exception for multiple hits of instruction TLB
See section 5, Exception Handling for details on the exception for multiple hits of the instruction
TLB. The exception for multiple hits of the instruction TLB does not make the level on the
RESETOUT pin low.
(5) Exception for multiple hits of data TLB
See section 5, Exception Handling for details on the exception for multiple hits of the data TLB.
The exception for multiple hits of the data TLB does not make the level on the RESETOUT pin
low.
Rev. 1.00 Sep. 19, 2007 Page 477 of 1136
REJ09B0359-0100