SH7730 Datasheet, PDF (621/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 20 I2C Bus Interface (IIC)
Section 20 I²C Bus Interface (IIC)
The I²C bus interface supports and provides a subset of the Philips I²C (Inter-IC) bus interface
functions. However, the configuration of the registers that control the I²C bus differs partly from
the Philips register configuration.
The I²C bus interface has 2 channels.
20.1 Features
• Supports master mode and slave mode
• Continuous transmission/reception
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization function
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
• Six interrupt sources
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
• Direct bus drive
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Rev. 1.00 Sep. 19, 2007 Page 573 of 1136
REJ09B0359-0100