SH7730 Datasheet, PDF (353/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Bit
6
5 to 2
1, 0
Section 11 Bus State Controller (BSC)
Initial
Bit Name Value R/W Description
WM
1
R/W External Wait Mask Specification
Specify whether or not the external wait input is valid.
The specification by this bit is valid even when the
number of access wait cycle is 0.
0: External wait is valid
1: External wait is ignored

All 0 R
Reserved
HW[1:0] 00
These bits are always read as 0. The write value should
always be 0.
R/W Number of Delay Cycles from RD/WEn Negation to
Address/CSn Negation
Specify the number of delay cycles from RD or WEn
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS4WCR, CS5AWCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — BAS —
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — SW[1:0]
WR[3:0]
WM — — — — HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 21 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Sep. 19, 2007 Page 305 of 1136
REJ09B0359-0100