SH7730 Datasheet, PDF (494/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 12 Direct Memory Access Controller (DMAC)
CKO
Bus cycle
DREQ
(Rising edge)
CPU
CPU
Burst acceptance
DMAC
DMAC
DACK
(High-active)
: Non-sensitive
period
Figure 12.14 Example of DREQ Input Detection in Burst Mode Edge Detection
CKO
Bus cycle
DREQ
(Overrun 0,
high-level)
DACK
(High-active)
CPU
CPU
1st acceptance
DMAC
2nd acceptance
Acceptance started
CKO
Bus cycle
DREQ
(Overrun 1,
high-level)
CPU
CPU
DMAC
1st acceptance
2nd acceptance
Non-sensitive period
DMAC
3rd acceptance
DACK
(High-active)
Acceptance started
Acceptance started
: Non-sensitive
period
Figure 12.15 Example of DREQ Input Detection in Burst Mode Level Detection
Rev. 1.00 Sep. 19, 2007 Page 446 of 1136
REJ09B0359-0100