SH7730 Datasheet, PDF (613/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 19 Compare Match Timer (CMT)
19.3.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether the individual compare match timer counters
(CMCNT_4 to CMCNT_0) operate or are halted.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
———————————
STR[4:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 5 
Initial
Value
All 0
4 to 0 STR[4:0] All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Count Start
Selects whether or not the individual compare match
timer counters (CMCNT_4 to CMCNT_0) operate or are
halted.
0: Halts counting by CMCNTn.
1: Runs counting by CMCNTn.
Note: n = 0 to 4 (channel number).
19.3.2 Compare Match Timer Control/Status Register (CMCSR)
Each CMCSR_n (n = 0 to 4) is a 16-bit register that indicates the occurrence of compare match or
overflow events for CMCNT_n, enables interrupts and DMA transfer requests, and sets up the
counter input clocks.
Do not change bits other than the CMF and OVF bits during the compare match timer counter
(CMCNT) operation.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CMF OVF — — — — CMS CMM — — CMR[1:0] —
CKS[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:R/(W)*R/(W)* R R R R R/W R/W R R R/W R/W R R/W R/W R/W
Rev. 1.00 Sep. 19, 2007 Page 565 of 1136
REJ09B0359-0100