SH7730 Datasheet, PDF (589/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 17 Realtime Clock (RTC)
Initial
Bit
Bit Name Value
R/W Description
1
RESET 0
R/W Reset
When 1 is written, initializes the divider circuit (RTC
prescaler and R64CNT). This bit always reads 0.
0: Runs normally.
1: Divider circuit is reset.
0
START 1
R/W Start Bit
Halts and restarts the counter (clock).
0: Second/minute/hour/day/week/month/year counter
halts.
1: Second/minute/hour/day/week/month/year counter
runs normally.
Note: The 64-Hz counter always runs unless stopped
with the RTCEN bit.
17.3.18 RTC Control Register 3 (RCR3)
When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The ENB bit in RYRAR is initialized by a power-on reset. Remaining fields of RCR3 are not
initialized by a power-on reset or manual reset, or in standby mode.
Bit: 7
6
5
4
3
2
1
0
ENB — — — — — — —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R
Bit
7
6 to 0
Bit Name
ENB
Initial
Value R/W
0
R/W

All 0 R
Description
When this bit is set to 1, comparison of the year alarm
register (RYRAR) and the year counter (RYRCNT) is
performed.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Sep. 19, 2007 Page 541 of 1136
REJ09B0359-0100