SH7730 Datasheet, PDF (758/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
22.5 SCIF Interrupt Sources and DMAC
The SCIF has four types of interrupt sources for each channel: transmit-FIFO-data-empty (TXI),
receive-error (ERI), receive-FIFO-data-full (RXI), and break (BRI). However, only a single
INTEVT code is assigned per channel, so interrupt sources must be identified by software. The
interrupt sources are enabled or disabled separately for each channel by means of the TIE, RIE,
and REIE bits in SCSCR.
When the TXI request is enabled by the TIE bit and the TDFE flag in SCFSR is set to 1, a TXI
interrupt request and transmit-FIFO-data-empty DMA transfer request are generated. When the
TXI request is disabled by the TIE bit and the TDFE flag in SCFSR is set to 1, only a transmit-
FIFO-data-empty DMA transfer request is generated. This transmit-FIFO-data-empty DMA
transfer request can activate the DMAC to perform data transfer.
When the RXI request is enabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set
to 1, an RXI interrupt request and receive-FIFO-data-full DMA transfer request are generated.
When the RXI request is disabled by the RIE bit and the RDF flag or the DR flag in SCFSR is set
to 1, only a receive-FIFO-data-full DMA transfer request is generated. This receive-FIFO-data-full
DMA transfer request can activate the DMAC to perform data transfer. Note that the RXI interrupt
request or receive-FIFO-data-full DMA transfer request resulting from the DR flag is only
generated in asynchronous mode.
When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI interrupt request is
generated.
To perform transmission/reception using the DMAC, configure and enable the DMAC first and
configure the SCIF next. The SCIF should be configured such that the RXI and TXI interrupt
requests are not sent to the interrupt controller. If not configured as such, the interrupt requests
sent to the interrupt controller will be cleared by the DMAC regardless of the interrupt handling
program.
Clearing the RIE bit to 0 and setting the REIE bit to 1 in SCSCR generates only an ERI interrupt
request without generating an RXI interrupt request.
Rev. 1.00 Sep. 19, 2007 Page 710 of 1136
REJ09B0359-0100