SH7730 Datasheet, PDF (311/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.4.3 IRL Interrupts
IRL interrupts are input via the IRL3 to IRL0 pins as level sense. When the values of the IRL3 to
IRL0 pins are 0 (B'0000), the highest level interrupt request (interrupt priority level 15) is
indicated. When the values of the pins are 15 (B'1111), no interrupt is requested (interrupt priority
level 0). Figure10.2 shows an example of connection for an IRL interrupt.
The IRL interrupt scheme includes a noise canceller function and the interrupt is detected when
the signal levels sampled at each peripheral module clock cycle are the same for consecutive 2
cycles. This prevents sampling of erroneous levels at transitions on the IRL pins. In standby mode,
a noise canceler is driven by the clock for the RTC because the supply of peripheral module clock
is stopped. Therefore, when the RTC is not used, recovering from standby mode by the IRL
interrupt cannot be executed.
The priority level provided by the IRL interrupt signals should be held until the interrupt handling
starts after the interrupt request has been accepted. However, changing to a higher priority level
will cause no problem.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by the IRL interrupt
handling.
When the LSH bit in ICR0 is 0, the interrupt request will be retained inside the LSI even when the
interrupt request from outside has been negated. The LSH bit should normally be set to 1.
This LSI
Interrupt request
Priority level
encode
4
IRL3 to IRL0
IRL3 to IRL0
Figure 10.2 Example of IRL Interrupt Connection
Rev. 1.00 Sep. 19, 2007 Page 263 of 1136
REJ09B0359-0100