SH7730 Datasheet, PDF (34/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Figure 18.6 Status Flag Clear Timing......................................................................................... 558
Section 19 Compare Match Timer (CMT)
Figure 19.1 Block Diagram of CMT .......................................................................................... 562
Figure 19.2 Counter Operation (One-Shot Operation) ............................................................... 569
Figure 19.3 Counter Operation (Free-Running Operation) ........................................................ 570
Figure 19.4 CMF Set Timing...................................................................................................... 571
Section 20 I2C Bus Interface (IIC)
Figure 20.1 Block Diagram of I²C Bus Interface ....................................................................... 574
Figure 20.2 External Circuit Connections of I/O Pins ................................................................ 575
Figure 20.3 I²C Bus Formats ...................................................................................................... 592
Figure 20.4 I²C Bus Timing........................................................................................................ 592
Figure 20.5 Master Transmit Mode Operation Timing (1)......................................................... 594
Figure 20.6 Master Transmit Mode Operation Timing (2)......................................................... 594
Figure 20.7 Master Receive Mode Operation Timing (1) .......................................................... 596
Figure 20.8 Master Receive Mode Operation Timing (2) .......................................................... 596
Figure 20.9 Slave Transmit Mode Operation Timing (1) ........................................................... 598
Figure 20.10 Slave Transmit Mode Operation Timing (2) ......................................................... 599
Figure 20.11 Slave Receive Mode Operation Timing (1)........................................................... 600
Figure 20.12 Slave Receive Mode Operation Timing (2)........................................................... 600
Figure 20.13 Block Diagram of Noise Filter .............................................................................. 601
Figure 20.14 Sample Flowchart for Master Transmit Mode ...................................................... 602
Figure 20.15 Sample Flowchart for Master Receive Mode ........................................................ 603
Figure 20.16 Sample Flowchart for Slave Transmit Mode......................................................... 604
Figure 20.17 Sample Flowchart for Slave Receive Mode .......................................................... 605
Figure 20.18 Bit Synchronous Circuit Timing ........................................................................... 607
Section 21 Serial I/O with FIFO (SIOF)
Figure 21.1 Block Diagram of SIOF .......................................................................................... 610
Figure 21.2 Serial Clock Supply................................................................................................. 639
Figure 21.3 Serial Data Synchronization Timing ....................................................................... 640
Figure 21.4 SIOF Transmit/Receive Timing .............................................................................. 641
Figure 21.5 Transmit/Receive Data Bit Alignment .................................................................... 643
Figure 21.6 Control Data Bit Alignment .................................................................................... 644
Figure 21.7 Control Data Interface (Slot Position)..................................................................... 645
Figure 21.8 Control Data Interface (Secondary FS) ................................................................... 646
Figure 21.9 Example of Transmit Operation in Master Mode.................................................... 649
Figure 21.10 Example of Receive Operation in Master Mode ................................................... 650
Figure 21.11 Example of Transmit Operation in Slave Mode .................................................... 651
Figure 21.12 Example of Receive Operation in Slave Mode ..................................................... 652
Figure 21.13 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 656
Rev. 1.00 Sep. 19, 2007 Page xxxiv of xlviii