SH7730 Datasheet, PDF (1026/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
Table 30.2 Register Status in Each Processing State
Register Name
Manual
Abbreviation Power-on Reset Reset
Match condition setting CBR0
register 0
H'20000000
Retained
Match operation setting CRR0
register 0
H'00002000
Retained
Match address setting
register 0
CAR0
Undefined
Retained
Match address mask
setting register 0
CAMR0
Undefined
Retained
Match condition setting CBR1
register 1
H'20000000
Retained
Match operation setting CRR1
register 1
H'00002000
Retained
Match address setting
register 1
CAR1
Undefined
Retained
Match address mask
setting register 1
CAMR1
Undefined
Retained
Match data setting
register 1
CDR1
Undefined
Retained
Match data mask setting CDMR1
register 1
Undefined
Retained
Execution count break
register 1
CETR1
Undefined
Retained
Channel match flag
register
CCMFR
H'00000000
Retained
Break control register CBCR
H'00000000
Retained
Sleep
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Standby
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
Retained
The access size must be the same as the control register size. If the size is different, the register is
not written to if attempted, and reading the register returns the undefined value. A desired break
may not occur between the time when the instruction for rewriting the control register is executed
and the time when the written value is actually reflected on the register. In order to confirm the
exact timing when the control register is updated, read the data which has been written most
recently. The subsequent instructions are valid for the most recently written register value.
Rev. 1.00 Sep. 19, 2007 Page 978 of 1136
REJ09B0359-0100