SH7730 Datasheet, PDF (1040/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
30.2.7 Execution Count Break Register 1 (CETR1)
CETR1 is a readable/writable 32-bit register which specifies the number of the channel hits before
a break occurs. A maximum value of 2¹² – 1 can be specified. When the execution count value is
included in the match conditions by using the match condition setting register, the value of this
register is decremented by one every time the channel is hit. When the channel is hit after the
register value reaches H'001, a break occurs.
Bit : _{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Initial value : ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: _{R R R R R R R R R R R R R R R R}
Bit : _{15 14 13 12 11 10 9}
8
7
6
5
4
3
2
1
0
CET
Initial value : ₀
0
0
0
R/W: _{R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W}
Initial
Bit
Bit Name Value R/W
31 to 12 —
All 0
R
11 to 0 CET
Undefined R/W
Description
Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
Execution Count
Specifies the execution count to be included in the break
conditions.
Rev. 1.00 Sep. 19, 2007 Page 992 of 1136
REJ09B0359-0100