SH7730 Datasheet, PDF (900/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 25 SIM Card Module (SIM)
RDRF
PER
nth transmit frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE
Retransmit frame
(n+1)th transmit frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Ds D0 D1 D2 D3 D4
(e)
(b)
(d)
(a)
(c)
Figure 25.8 Retransmission when Smart Card Interface is in Receive Mode
• Retransmission when the smart card interface is in transmit mode (T = 0)
Figure 25.9 shows retransmit operations when the smart card interface is in transmit mode.
(a) After completion of transmission of one frame, if an error signal is returned from the
receive side, the ERS bit in SCSSR is set to 1. If the RIE bit in SCSCR is set to enable, an
ERI request is issued. The ERS bit in SCSSR should be cleared to 0 before the sampling
timing for the next parity bit.
(b) In T = 0 mode, the TEND bit in SCSSR is not set for a frame when an error signal
indicating an error is received.
(c) If no error signal is returned from the receive side, the ERS bit in SCSSR is not set.
(d) If no error signal is returned from the receive side, it is assumed that transmission of one
frame, including retransmission, is completed. If SCTDR is not empty at this time, the
TEND bit in SCSSR is set to 1. At this time, if the TEIE bit in SCSCR is set to enable, a
TEI interrupt request is issued.
nth transmit frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP DE
Retransmit frame
(n+1)th transmit frame
(DE)
Ds D0 D1 D2 D3 D4 D5 D6 D7 DP
Ds D0 D1 D2 D3 D4
TDRE
Transmission from SCTDR to SCTSR
TEND
(b)
ERS
(a)
Transmission from SCTDR to SCTSR
(d)
(c)
Figure 25.9 Retransmit Standby Mode (Clock Stopped)
when Smart Card Interface is in Transmit Mode
Rev. 1.00 Sep. 19, 2007 Page 852 of 1136
REJ09B0359-0100