SH7730 Datasheet, PDF (816/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
23.5 Interrupt Sources and DMAC
In asynchronous mode, the SCIFA supports six interrupts: transmit-FIFO-data-empty, transmit
data stop, receive-error, receive-FIFO-data-full, break receive, and receive data ready. A common
interrupt vector is assigned to each interrupt source.
In synchronous mode, the SCIFA supports two interrupts: transmit-FIFO-data-empty and receive-
FIFO-data-full.
Table 23.7 shows the interrupt sources. The interrupt sources are enabled or disabled by means of
the TIE, RIE, ERIE, BRIE, DRIE, and TSIE bits in SCASCR.
When the TDFE flag in SCASSR is set to 1, the transmit-FIFO-data-empty interrupt request is
generated. When the TSF flag in SCASSR is set to 1, the transmit-data-stop interrupt request is
generated. Activating the DMAC and transferring data can be performed by the transmit-FIFO-
data-empty interrupt and data stop interrupt requests. The DMAC transfer request is automatically
cleared when the number of data bytes written to SCAFTDR by the DMAC is increased more than
that of setting transmit triggers.
When the RDF flag in SCASSR is set to 1, a receive-FIFO-data-full interrupt request is generated.
Activating the DMAC and transferring data can be performed by the receive-FIFO-data-full
interrupt request. The DMAC transfer request is automatically cleared when receive data is read
from SCAFRDR by the DMAC until the number of receive data bytes in SCAFRDR is decreased
less than that of receive triggers.
When executing the data transmission/reception using the DMAC, configure the DMAC first and
enable it, then configure the SCIFA. The completion of the DMA transfer is the completion of
transmission/reception.
An interrupt request is generated when the ER flag in SCASSR is set to1; the BRK flag in
SCASSR is set to 1; the DR flag in SCASSR is set to 1; or the TSF flag in SCASSR is set to 1. A
common interrupt vector is assigned to each interrupt source. The activation of DMAC and
generation of an interrupt are not executed at the same time by the same source. The DMAC
should be activated according to the following procedure.
1. Set the interrupt enable bit (TIE, RIE, or TDIE) corresponding to the generated interrupt
source to 1.
2. Mask the corresponding interrupt request by the interrupt mask register of the interrupt
controller.
Rev. 1.00 Sep. 19, 2007 Page 768 of 1136
REJ09B0359-0100