SH7730 Datasheet, PDF (282/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 8 Caches
8.7.3 Transfer to External Memory
Transfer from the SQs to external memory can be performed with a prefetch instruction (PREF).
Issuing a PREF instruction for addresses H'E000 0000 to H'E3FF FFFC in the P4 area starts a
transfer from the SQs to external memory. The transfer length is fixed at 32 bytes, and the start
address is always at a 32-byte boundary. While the contents of one SQ are being transferred to
external memory, the other SQ can be written to without a penalty cycle. However, writing to the
SQ involved in the transfer to external memory is kept waiting until the transfer is completed.
The physical address bits [28:0] of the SQ transfer destination are specified as shown below,
according to whether the MMU is enabled or disabled.
• When MMU is enabled (AT = 1 in MMUCR)
The SQ area (H'E000 0000 to H'E3FF FFFF) is set in VPN of the UTLB, and the transfer
destination physical address in PPN. The ASID, V, SZ, SH, PR, and D bits have the same
meaning as for normal address translation, but the C and WT bits have no meaning with regard
to this page. When a prefetch instruction is issued for the SQ area, address translation is
performed and physical address bits [28:10] are generated in accordance with the SZ bit
specification. For physical address bits [9:5], the address prior to address translation is
generated in the same way as when the MMU is disabled. Physical address bits [4:0] are fixed
at 0. Transfer from the SQs to external memory is performed to this address.
• When MMU is disabled (AT = 0 in MMUCR)
The SQ area (H'E000 0000 to H'E3FF FFFF) is specified as the address at which a PREF
instruction is issued. The meanings of address bits [31:0] are as follows:
[31:26]
[25:6]
[5]
: 111000
: Address
: 0/1
[4:2] : Don't care
[1:0] : 00
Store queue specification
Transfer destination physical address bits [25:6]
0: SQ0 specification
1: SQ1 specification and transfer destination physical
address bit [5]
No meaning in a prefetch
Fixed at 0
Physical address bits [28:26], which cannot be generated from the above address, are generated
from QACR0 and QACR1.
QACR0[4:2] : Physical address bits [28:26] corresponding to SQ0
QACR1[4:2] : Physical address bits [28:26] corresponding to SQ1
Rev. 1.00 Sep. 19, 2007 Page 234 of 1136
REJ09B0359-0100