SH7730 Datasheet, PDF (41/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Tables
Section 1 Overview
Table 1.1 Features of This LSI ................................................................................................. 2
Table 1.2 Pin Assignment ....................................................................................................... 11
Table 1.3 Pin Functions .......................................................................................................... 19
Table 1.4 Product Lineup........................................................................................................ 27
Section 2 Programming Model
Table 2.1 Initial Register Values............................................................................................. 32
Table 2.2 Bit Allocation for FPU Exception Handling........................................................... 42
Section 3 Instruction Set
Table 3.1 Execution Order of Delayed Branch Instructions ................................................... 50
Table 3.2 Addressing Modes and Effective Addresses........................................................... 51
Table 3.3 Notation Used in Instruction List............................................................................ 56
Table 3.4 Fixed-Point Transfer Instructions ........................................................................... 57
Table 3.5 Arithmetic Operation Instructions .......................................................................... 59
Table 3.6 Logic Operation Instructions .................................................................................. 61
Table 3.7 Shift Instructions..................................................................................................... 62
Table 3.8 Branch Instructions ................................................................................................. 63
Table 3.9 System Control Instructions.................................................................................... 63
Table 3.10 Floating-Point Single-Precision Instructions .......................................................... 66
Table 3.11 Floating-Point Double-Precision Instructions......................................................... 67
Table 3.12 Floating-Point Control Instructions ........................................................................ 68
Table 3.13 Floating-Point Graphics Acceleration Instructions ................................................. 68
Section 4 Pipelining
Table 4.1 Representations of Instruction Execution Patterns.................................................. 70
Table 4.2 Instruction Groups .................................................................................................. 80
Table 4.3 Combination of Preceding and Following Instructions........................................... 82
Table 4.4 Issue Rates and Execution Cycles........................................................................... 84
Section 5 Exception Handling
Table 5.1 Register Configuration............................................................................................ 93
Table 5.2 States of Register in Each Operating Mode ............................................................ 94
Table 5.3 Exceptions............................................................................................................. 100
Table 5.4 UTLB Protection Information (TLB Compatible Mode)...................................... 111
Table 5.5 UTLB Protection Information (TLB Extended Mode) ......................................... 111
Table 5.6 ITLB Protection Information (TLB Compatible Mode) ....................................... 113
Table 5.7 ITLB Protection Information (TLB Extended Mode)........................................... 113
Rev. 1.00 Sep. 19, 2007 Page xli of xlviii