SH7730 Datasheet, PDF (735/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Bit
10 to 8
7, 6
Bit Name
Initial
Value R/W
RSTRG[2:0] 000 R/W
RTRG[1:0] 00
R/W
Description
RTS Output Active Trigger
When the quantity of receive data in SCFRDR becomes
more than the number shown below, RTS signal is set to
high.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Receive FIFO Data Trigger
Set the quantity of receive data at which the receive data
full (RDF) flag in SCFSR is set. The RDF flag is set to 1
when the quantity of receive data stored in SCFRDR has
become equal to or more than the set trigger number
shown below as the reception proceeds.
• Asynchronous mode • Clock synchronous mode
00: 1
01: 4
10: 8
11: 14
00: 1
01: 2
10: 8
11: 14
Rev. 1.00 Sep. 19, 2007 Page 687 of 1136
REJ09B0359-0100