SH7730 Datasheet, PDF (1053/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 30 User Break Controller (UBC)
With the above settings, the user break occurs after executing the instruction at address
H'00037226 where ASID is H'80 before executing the instruction at address H'0003722E
where ASID is H'70.
• Example 1-3
Register settings: CBR0 = H'00000013 / CRR0 = H'00002001 / CAR0 = H'00027128 /
CAMR0 = H'00000000 / CBR1 = H'00000013 / CRR1 = H'00002001 / CAR1 = H'00031415 /
CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H'00000000 / CBCR = H'00000000
Specified conditions: Independent for channels 0 and 1
 Channel 0
Address: H'00027128 / Address mask: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
ASID is not included in the conditions.
 Channel 1
Address: H'00031415 / Address mask: H'00000000
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
ASID, data values, and execution count are not included in the conditions.
With the above settings, the user break occurs for channel 0 before executing the instruction at
address H'00027128. No user break occurs for channel 1 since the instruction fetch is executed
only at even addresses.
• Example 1-4
Register settings: CBR0 = H'40800013 / CRR0 = H'00002000 / CAR0 = H'00037226 /
CAMR0 = H'00000000 / CBR1 = H'C0700013 / CRR1 = H'00002001 / CAR1 = H'0003722E /
CAMR1 = H'00000000 / CDR1 = H'00000000 / CDMR1 = H'00000000 / CETR1 =
H′00000000 / CBCR = H'00000000
Specified conditions: Channel 0 → Channel 1 sequential mode
 Channel 0
Address: H'00037226 / Address mask: H'00000000 / ASID: H'80
Bus cycle: Instruction fetch (before executing the instruction)
 Channel 1
Address: H'0003722E / Address mask: H'00000000 / ASID: H'70
Data: H'00000000 / Data mask: H'00000000 / Execution count: H'00000000
Bus cycle: Instruction fetch (before executing the instruction)
Data values and execution count are not included in the conditions.
Rev. 1.00 Sep. 19, 2007 Page 1005 of 1136
REJ09B0359-0100