SH7730 Datasheet, PDF (262/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 8 Caches
8.2.3 Queue Address Control Register 1 (QACR1)
QACR1 specifies the area onto which store queue 1 (SQ1) is mapped when the MMU is disabled.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
AREA1
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
00
R/W: R R R R R R R R R R R R/W R/W R/W R R
Bit
31 to 5
4 to 2
1, 0
Initial
Bit Name Value
R/W

All 0
R
AREA1 Undefined R/W

All 0
R
Description
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
When the MMU is disabled, these bits generate
physical address bits [28:26] for SQ1.
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
Rev. 1.00 Sep. 19, 2007 Page 214 of 1136
REJ09B0359-0100