SH7730 Datasheet, PDF (785/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 23 Serial Communication Interface with FIFO A (SCIFA)
Initial
Bit
Bit Name
Value R/W Description
0
DR
0
R/(W)* Receive Data Ready
Indicates that SCAFRDR stores data which is less than
the specified reception trigger number, and that next
data is not yet received after 15 etu has elapsed from
the last stop bit in asynchronous mode.
0: Receive is in progress, or no received data remains
in SCAFRDR after the receive ended normally.
[Clearing conditions] (Initial value)
• Power-on reset
• All receive data in SCAFRDR is read, and DR is
read as 1, then written to with 0.
1: Next receive data is not received
[Setting condition]
• SCAFRDR stores the data which is less than the
specified reception trigger number, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the 8-
bit 1-stop-bit format. (etu: Element Time
Unit)
Note: * The only value that can be written is 0 to clear the flag.
Rev. 1.00 Sep. 19, 2007 Page 737 of 1136
REJ09B0359-0100