SH7730 Datasheet, PDF(149/1188 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

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SH7730 Datasheet, PDF (149/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

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Section 5 Exception Handling

Exception Transition

Direction*3

Exception Execution

Category Mode

Exception

Priority Priority Vector

Level*2 Order*2 Address

Offset

Exception

Code*4

General Completion Unconditional trap (TRAPA) 2

exception type

User break after instruction

2

execution*

Interrupt Completion Nonmaskable interrupt

3

type

General interrupt request

4

4

(VBR)

H'100

H'160

10

(VBR/DBR) H'100/â H'1E0

â

(VBR)

H'600

H'1C0

â

(VBR)

H'600

â

Note:

1. When UBDE in CBCR = 1, PC = DBR. In other cases, PC = VBR + H'100.

2. Priority is first assigned by priority level, then by priority order within each level (the

lowest number represents the highest priority).

3. Control passes to H'A000 0000 in a reset, and to [VBR + offset] in other cases.

4. Stored in EXPEVT for a reset or general exception, and in INTEVT for an interrupt.

Rev. 1.00 Sep. 19, 2007 Page 101 of 1136

REJ09B0359-0100

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