SH7730 Datasheet, PDF (299/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 10 Interrupt Controller (INTC)
10.3.2 Interrupt Control Register 1 (ICR1)
ICR1 specifies the detection mode for the external interrupt input pins IRQ7 to IRQ0 individually:
rising edge, falling edge, low level, or high level.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IRQ0S
IRQ1S
IRQ2S
IRQ3S
IRQ4S
IRQ5S
IRQ6S
IRQ7S
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15, 14
Initial
Bit Name Value R/W
IRQ0S 00
R/W
13, 12 IRQ1S 00
R/W
11, 10 IRQ2S 00
R/W
9, 8
IRQ3S 00
R/W
7, 6
IRQ4S 00
R/W
5, 4
IRQ5S 00
R/W
3, 2
IRQ6S 00
R/W
1, 0
IRQ7S 00
R/W
Description
IRQn Sense Select
These bits select whether interrupt request signals
corresponding to pins IRQ7 to IRQ0 are detected by a
rising edge, falling edge, low level, or high level.
IRQnS
00
01
Detection Mode
Interrupt request is detected on falling
edge of IRQn input
Interrupt request is detected on rising
edge of IRQn input
10
Interrupt request is detected on low
level of IRQn input
11
Interrupt request is detected on high
level of IRQn input
[Legend] n = 0 to 7
Rev. 1.00 Sep. 19, 2007 Page 251 of 1136
REJ09B0359-0100