SH7730 Datasheet, PDF (1127/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 33 Electrical Characteristics
Td1
Td2
Td3
Td4
Td5
Td6
Td7
Td8
Tr
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tde
Tap
CKO
A23 to A0
A12/A11*¹
CSn
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
tAD1
Row
Column Column Column Column Column Column Column
Address Address1 Address2 Address3 Address4 Address5 Address6 Address7
Column
Address8
tAD1
tAD1
tAD1
tAD1
tCSD1
READA
Command
READA
Command
tCSD1
RDWR
RAS
CAS
DQMx
tRWD1
tRASD1
tRASD1
tCASD1
tCASD1
tDQMD1
tCASD1
tDQMD1
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
tRDS2
D15 to D0
tBSD
BS
tRDH2
tRDH2
tRDH2
tRDH2
tRDH2
tRDH2
tBSD
tRDH2
tRDH2
CKE
tDACD
(High)
tDACD
DACKn*²
Notes: 1. Address pin that is connected to A10 of SDRAM.
2. Waveform when active low is specified for DACKn.
tAD1
tAD1
tRWD1
tRASD1
tCASD1
Figure 33.19 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycles, TRP = 1 Cycle)
Rev. 1.00 Sep. 19, 2007 Page 1079 of 1136
REJ09B0359-0100