SH7730 Datasheet, PDF (718/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 22 Serial Communication Interface with FIFO (SCIF)
Bit
15 to 8
Bit Name

7
CA
6
CHR
5
PE
Initial
Value
All 0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Communication Mode
Selects whether the SCIF operates in asynchronous or
clock synchronous mode.
0: Asynchronous mode
1: Clock synchronous mode
R/W Character Length
Selects 7-bit or 8-bit data length in asynchronous mode.
When 7-bit data is selected, the MSB (bit 7) of the
transmit FIFO data register is not transmitted. In clock
synchronous mode, the data length is always 8 bits,
regardless of the CHR setting.
0: 8-bit data
1: 7-bit data
R/W Parity Enable
Selects whether to add a parity bit to transmit data and
to check the parity of receive data, in asynchronous
mode. In clock synchronous mode, a parity bit is neither
added nor checked, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked*
Note: * When PE is set to 1, an even or odd parity
bit is added to transmit data, depending on
the parity mode (OE) setting. Receive data
parity is checked according to the even/odd
(OE) mode setting.
Rev. 1.00 Sep. 19, 2007 Page 670 of 1136
REJ09B0359-0100