SH7730 Datasheet, PDF (366/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
9

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
8, 7
A3CL[1:0] 10
R/W CAS Latency for Area 3.
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
When connecting the SDRAM to area 2 and area 3, set
the CAS latency to the bits 8 and 7 in the CS2WCR
register and the SDMR2 and SDMR3 registers for
SDRAM mode setting. (See table 11.22.)
6

1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
5

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
4, 3
TRWL[1:0] 00
R/W Number of Cycles from WRITA/WRIT Command to
Auto-Precharge/PRE Command
Specifies the number of cycles from issuing
WRITA/WRIT command to the start of auto-precharge
or to issuing PRE command. The setting for areas 2
and 3 is common.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 1.00 Sep. 19, 2007 Page 318 of 1136
REJ09B0359-0100