SH7730 Datasheet, PDF (391/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 11.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKO at the transition from the T1 or Tw
cycle to the T2 cycle.
Wait states inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
CKO
A25 to A0
CSn
Read
RDWR
RD
D31 to D0
RDWR
Write
WEn
D31 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 11.10 Wait State Timing for Normal Space Access
(Wait State Insertion using WAIT Signal)
Rev. 1.00 Sep. 19, 2007 Page 343 of 1136
REJ09B0359-0100