SH7730 Datasheet, PDF (384/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 11 Bus State Controller (BSC)
11.5.2 Normal Space Interface
(1) Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be connected. When using SRAM with a byte-selection pin, see section
11.5.7, Byte-Selection SRAM Interface. Figure 11.3 shows the basic timings of normal space
access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one
cycle to indicate the start of a bus cycle.
CKO
T1
T2
A25 to A0
CSn
RDWR
Read _RD
D15 to D0
RDWR
Write
WEn
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 11.3 Normal Space Basic Access Timing (Access Wait 0)
Rev. 1.00 Sep. 19, 2007 Page 336 of 1136
REJ09B0359-0100