SH7730 Datasheet, PDF (53/1188 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7780 Series

Section 1 Overview
Item
Features
Direct memory •
access controller
(DMAC)
•
Six channels, two channels of which (channels 0, 1) support external
requests
Address space: 4 Gbytes on architecture
• Data transfer length: Byte, word (2 bytes), longword (4 bytes), 8 bytes,
16 bytes, and 32 bytes
• Maximum number of transfer times: 16,777,216 times
• Address mode: Dual address mode
• Transfer request: Selectable from external request, on-chip peripheral
module request, and auto request
• Bus mode: Selectable from cycle stealing mode (normal mode and
intermittent mode) and burst mode
• Priority: Selectable between fixed channel priority mode and round-robin
mode
• Interrupt request: Generates an interrupt request to the CPU at the end of
data transfer
• Repeat function: Automatically re-sets the transfer source, destination, and
number of transfers at the end of DMA transfer
• Reload function: Automatically re-sets the transfer source and destination at
the end of the specified number of DMA transfers
• External request detection: Selectable from low-level/high-level detection or
rise/fall detection of the DREQ input
• Transfer request acknowledge signals: Active level is selectable for DACK
and TEND
Rev. 1.00 Sep. 19, 2007 Page 5 of 1136
REJ09B0359-0100